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ASML to Work With Chipmakers on High NA EUV Tools for Larger Data Center Chips
ASML is moving to solve one of the more overlooked bottlenecks in the AI chip supply chain, and it is doing so by working directly with the companies that will eventually use its most advanced machines. The Dutch lithography giant said this week that it plans to collaborate with major chipmakers to adapt its next-generation High NA EUV tools so they can print chips as large as today’s biggest data center processors, a shift that could reshape how quickly the industry scales up production of the chips powering the AI boom.
To understand why this matters, it helps to know what ASML’s machines actually do. The company makes lithography tools, which print chip patterns onto silicon wafers by shining light through a mask that carries the design of the chip. Its current generation of extreme ultraviolet, or EUV, tools is already the backbone of advanced chip manufacturing worldwide, and those machines can print a chip up to about 800 square millimeters, a limit that companies like Nvidia and Google already design their largest processors around. That 800 square millimeter ceiling is not arbitrary. It reflects the physical size of the mask used in current EUV systems, and chip designers have essentially been building their most powerful data center processors right up against that boundary for years.
ASML’s newer High NA EUV tools were built to print much finer circuit features, which is exactly what chipmakers need as they push toward smaller and more densely packed transistors. But there has been a catch. Because these newer machines use a smaller mask than the current generation of EUV tools, they have so far been limited to printing smaller chips, even though their resolution is superior. That has kept High NA tools mostly confined to more compact applications rather than the enormous processors used in AI data centers. Intel is currently the only major chipmaker using ASML’s newest High NA tools in actual production, and it has been using them for laptop chips rather than large-scale data center silicon.
The fix ASML is now pursuing is straightforward in concept, even if it will take years to execute. The company plans to move to a larger mask size for its High NA machines, which would let them print chips as large as today’s biggest data center processors while retaining the finer feature resolution that makes High NA valuable in the first place. According to ASML, that transition is meant to encourage broader adoption of the technology across high-volume commercial manufacturing, since right now High NA tools are not yet used for high-volume production at either Taiwan Semiconductor Manufacturing Company or Samsung Electronics, the two companies that dominate advanced chip fabrication globally.
That is where the collaboration piece becomes important. ASML cannot make this transition alone, since the entire point of the shift is to align mask sizes and manufacturing processes across the companies that will actually buy and operate these machines. SK Hynix has confirmed it is evaluating participation in the consortium working on introducing 12-inch masks, and the memory chipmaker said it is targeting 2028 to apply High NA EUV processes to DRAM mass production specifically. TSMC has said it plans to bring ASML’s High NA technology into advanced-node, high-volume production starting in 2030, while Samsung has also indicated plans to introduce the technology, though on a somewhat different timeline. Taken together, these commitments suggest the industry’s biggest chipmakers see enough long-term value in larger-format High NA tools to start planning their fabrication roadmaps around a technology that will not reach full commercial scale for years.
ASML’s own timeline reflects that reality. The company is targeting pilot production lines using the new larger-mask High NA tools by 2031, with full high-volume commercial manufacturing readiness expected by 2033. That is a long runway, even by semiconductor industry standards, where equipment development cycles routinely stretch across most of a decade. But the payoff, according to ASML, could be substantial. Marco Pieters, ASML’s chief technology officer, told Reuters that if the industry manages to execute this transition collectively, the productivity of these systems could increase by roughly 40 percent, a meaningful gain for an industry where wafer throughput directly affects how quickly companies like Nvidia can scale production of the GPUs and accelerators driving the current AI infrastructure buildout.
That AI angle is really the reason this development matters beyond the semiconductor equipment industry itself. Nvidia and other data center chip designers have been pushing the physical limits of what current EUV tools can print for several product generations now, and demand for AI accelerators has only intensified that pressure. If chip sizes are effectively capped by lithography mask limits rather than by what chip architects actually want to build, that constraint eventually shows up as a ceiling on how much computing power a single chip can pack in, forcing companies toward more complex multi-chip packaging solutions instead. ASML’s move to expand High NA mask size directly targets that constraint, giving chip designers more room to work with once the technology matures.
For now, none of this changes anything about chip production in the near term. Intel remains the sole High NA production customer today, and the broader industry shift toward larger-format High NA tools will play out gradually over the next several years as ASML, TSMC, Samsung, SK Hynix, and other partners work through the engineering and standardization challenges involved. But the announcement signals where the entire lithography ecosystem is heading, and it gives a clearer picture of the timeline the industry is working against as AI chip demand continues to outpace the physical limits of current manufacturing tools.
